Architecture design, VHDL coding and simulation of frame buffer manager portion of a Digital Video Recorder system using Altera FLEX FPGAs with Leonardo Spectrum VHDL synthesis and Altera Quartus-II place and route tools.
	Architecture design, VHDL coding, simulation, and lab debugging for a Xilinx Virtex-E XCV600E FPGA running at 66 and 132 MHz using Synplicity, Xilinx, and Model Technology tools. Used in a Voice over IP product.
	Chip architecture and VHDL design and simulation for portions of 2 CMOS standard cell ASICs using Synopsys, Model Technology, code coverage, and formal verification tools. Gate counts were 250k+ with design rules of 0.25 micron or smaller. Chips were used in a multi-gigabit ATM switch. Fab was IBM.
	Architecture design and vendor selection for an estimated 200k gate CMOS standard cell ASIC targeted for a multi-gigabit ATM switch. Fab was to be ST. Project was canceled just as coding began.
	System design and VHDL design and simulation of 22000-gate, 0.8 micron CMOS gate array ASIC following prototyping in Xilinx FPGAs using Synopsys, Model Technology, and Xilinx tools. Fab was AMI.
	Schematic design and simulation of a 9200-gate, 1.0 micron CMOS gate array ASIC using Viewlogic tools. Fab was AMI.

	Synopsys Design Compiler ASIC VHDL synthesis (Sun)
	Synplicity FPGA VHDL synthesis (PC)
	Leonardo FPGA VHDL synthesis (PC)
	Model Technology VHDL simulation (PC and Sun)
	VHDLCover code coverage (Sun)
	Chrysalis formal verification (Sun)
	Verisity Specman E VHDL verification (Sun). Course taken but not used.
	Altera Quartus II (PC) place and route tools
	Xilinx ISE (PC and Sun) place and route tools
	Protel schematic and PCB layout (PC)
	Viewlogic synthesis and schematic (PC and Sun)
	Timing Designer (PC and Sun)
	Abel (VAX)